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TDA7501
Line driver for digital car radio Signal processor (DSPLD)
Features
Inputs: - Quasi differential stereo input for CD - Differential stereo inputs for phone, navigation, FM, AM - Single-ended input for cassette- four independent input multiplexer and gain stages - Envelope-detector for AM noise-blanking - Mixing of phone and navigation - DC connection to DSP - Dual MPX inputs Outputs: - 6 Output channels with independent volume control - 4 Main output channels with additional input selector for phone and/or navigation or CD - Outputs level up to 4V rms - AC connection from DSP Digital control: - SPI bus or I2C bus interface (selectable) - Direct mute for the output stages and/or high impedance mpx mute
LQFP44
Description
The line driver handles all analog input and output signals for the digital car radio signal processor TDA7501. The device contains four independent input multiplexers to select the sources for the DSP's four AD converters. Four additional gain stages allow an adaptation to run the ADCs in best S/N condition. The six outputs have independent volume stages with a large dynamic range. Using a 12V supply the outputs are able to drive up to 4Vrms .
Order codes
Part number TDA7501 TDA7501TR Package LQFP44 (10 x 10 x 1.4 mm) LQFP44 (10 x 10 x 1.4 mm) Packing Tray Tape and Reel
January 2007
Rev 5
1/29
www.st.com 1
Contents
TDA7501
Contents
1 2 3 Block diagram and pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description of the input part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 3.2 3.3 3.4 Input Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Dual MPX mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Additional quasi differential Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Transfer function of the AM/FM level inputs . . . . . . . . . . . . . . . . . . . . . . . 12
4
Description of the output part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 4.2 Overall gain structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Speaker (linedriver) outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Reference concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 5.2 Dual supply mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Single supply mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 7
Digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8
I2C bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9
Software specification for both modes . . . . . . . . . . . . . . . . . . . . . . . . . 19
9.1 9.2 9.3 Auto increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10 11
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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TDA7501
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Switching characteristics (SPI mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input selector 1L..3R, bits D7 ..D3 (subaddresses 0..3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Input selector 1L, bits D2 ..D0 (subaddresses 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Input selector 1R, bits D2 ..D0 (subaddresses 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Input selector 2L, bits D2 ..D0 (subaddresses 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Input selector 2R, bits D2 ..D0 (subaddresses 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Phone navigation (subaddress 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Mode select (subaddress 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Configuration (subaddress 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Output selector (subaddress 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Volume speaker outputs (subaddresses 8...13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FM level range (subaddress 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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List of figures
TDA7501
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Input part. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Quasi differential input-stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Mono differential input-stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Differential input-stage for AM/FM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block diagram Dual MPX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Additional quasi differential input simplified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AM/FM level inputs transfer function (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output part. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Level diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Speaker (Linedriver) outputs simplified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reference voltage generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Timing diagram for the SPI bus mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Timing diagram for switching characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Test board diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 LQFP44 (10x10) mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 27
4/29
TDA7501
Block diagram and pin connections
1
Block diagram and pin connections
Figure 1. Block diagram
Figure 2.
Pin connection (top view)
OUT1R OUT1L OUT2L ADCVDDREF OUT2R
IN1R
IN2R
44
43
42
41
40
IN1L
39
38
IN2L
37
36
IN3L
35
IN3R
34 33 32 31 30 29 28 27 26 25 24 23
V33 SIGGND CassL CassR CDL+ CDSTEREO FULL DIFFERENTIAL * IC MONO DIFFERENTIAL *
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
MUTE SDA SCL SEL SPKR1L SPKR1R SPKR2L SPKR2R SPKR3L SPKR3R OUTPUTREF
CDR+ PHONE+ PHONENAVINAVI+
QUASI DIFFERENTIAL
IAM-LEVEL
PHFM-LEVEL
FM
TUNER-
AM
MPX-RDS
AM-IF
GND
VDD
VCC
PGND
D00AU1200/A
5/29
Electrical specifications
TDA7501
2
Electrical specifications
Table 1.
Symbol Vdd VP IS8 IS12 SVRR
Supply
Parameter Supply voltage Output supply voltage Supply current Vdd Supply current VP Ripple rejection @ 1kHz Vdd = 8.3V VP = 12V Test condition Min. 7.5 Typ. 8.3 12 27 5 60 Max. 10 Unit V V mA mA dB
Table 2.
Symbol VDDmax VSmax Tamb Tstg
Absolute maximum ratings
Parameter Operating supply voltage VDD Operating supply voltage Vs Operating temperature range Storage temperature range Value 10.5 13.0 -40 to 85 -55 to +150 Unit V V C C
Table 3.
Symbol Rth j-pins
Thermal data
Parameter Thermal Resistance Junction-pins Max. Value 65 Unit C/W
ESD:
All pins are protected against ESD according to the MIL883 standard. Table 4. Electrical characteristcs (VDD = VS = 8.3V; V33 = 3.3V Tamb = 25C; RL = 10k; all gains = 0dB; f = 1kHz; unless otherwise specified)
Parameter Test condition Min. Typ. Max. Unit
Symbol General VCL SIN GIN MIN GIN MAX GSTEP VDC dIN
Input clipping level Input separation Min. input gain - input part Max. input gain - input part Max. input gain - output part Step resolution Adjacent gain steps DC steps GMIN to GMAX Distortion VOUT = 0.7VRMS all stages 0dB Volume 0dB 80
2.3 100 0 15 12 1 0.5 5 0.00 2 0.08
VRMS dB dB dB dB dB mV mV %
6/29
TDA7501 Table 4.
Electrical specifications Electrical characteristcs (continued) (VDD = VS = 8.3V; V33 = 3.3V Tamb = 25C; RL = 10k; all gains = 0dB; f = 1kHz; unless otherwise specified)
Parameter Output DC-voltage Output impedance OUT1L, 1R Rout Output impedance OUT2L, 2R Test condition pins 41..44 pins 43..44 pins 41..42 Min. Typ. 1.65 300 3 Max. Unit V W k
Symbol VDCout
Quasi differential CD stereo input (non inverting) Rin CMRR VN Input resistance (see Fig. 2) Common mode rejection ratio Output noise Differential VCM = 1VRMS @ 1kHz VCM = 1VRMS @ 10kHz 20Hz - 20kHz; unweighted 70 45 45 100 70 60 2.0 130 k dB dB V
Differential phone/navigation/FM/AM input (inverting) Rin CMRR VN Input resistance (see Fig. 3) Common mode rejection ratio Output noise VCM = 1VRMS @ 1kHz VCM = 1VRMS @ 10kHz 20Hz - 20kHz; unweighted 35 40 40 50 70 60 2.0 65 k dB dB V
AM IF input Rin Input resistance 35 50 65 k
Cassette input (non inverting) Rin VN Input resistance Output noise 20Hz - 20kHz; unweighted 70 100 2.0 130 k V
AM/FM level input Rin Vmin Vmax Input resistance Minimum input voltage Maximum input voltage 70 -0.4 7.0 100 130 k V V
Dual MPX control (pin tuner-) VCTRLMPX1 Control voltage for MPX 1+2 VCTRLMPX2 Control voltage for MPX2 VCTRLMPX3 Control voltage for MPX 1+2 VCTRLMPX4 Control voltage for MPX1 Speaker outputs RLOAD = 10KW (AC) Rin GMAX Input impedance Max. gain external reference mode 35 50 33 65 k dB MPX1 -> MPX1 + MPX2 MPX1 + MPX1 -> MPX2 MPX2 -> MPX1 + MPX2 MPX1 + MPX2 -> MPX2 1.5 4.0 3.5 1.0 V V V V
7/29
Electrical specifications Table 4.
TDA7501
Electrical characteristcs (continued) (VDD = VS = 8.3V; V33 = 3.3V Tamb = 25C; RL = 10k; all gains = 0dB; f = 1kHz; unless otherwise specified)
Parameter Max. attenuation Test condition internal reference mode Min. Typ. -73 1 80 from +15 to -40dB Adjacent attenuation steps internal reference mode 0.3 4.15 outre f 2.3 2.8 4 5 10 40 BW = 20Hz-20kHz muted0dB muted 6dB gain = 0dB gain = 6dB BW = 20Hz-20kHz VO = 2VRMS VO = 4VRMS VOUT = 1VRMS; all stages 0dB 80 80 3.0 7.5 10 13 106 110 0.00 5 100 100 0.08 120 100 2 3 Max. Unit dB dB dB dB mV V V VRMS VRMS VRMS k nF W V V V V dB dB % dB dB
Symbol ATTMAX
ATTSTEP Step resolution ATTMUTE Output mute attenuation EE VDC VDCOUT Attenuation set error DC steps
Output DC voltage external reference mode d = 0.3%, VCC = VDD = 8.3V gain = 0dB gain = 6dB d = 0.3%, VCC = 12V VDD = 8.3V gain = 6dB
VCLIP
Output clipping level
RL CL ROUT
Output load resistance Output load capacitance Output impedance
AC coupled
VN
Output noise
S/N
Signal to noise ratio
dout SC X
Distortion Channel separation left/right Crosstalk
ADCVDDREF (CODEC reference) Imaxadc Max. output current pin 40 5 mA
BUS INPUTS Vlow Vhigh Vth_SPI Voltage for logic "0 Voltage for logic "1 SPI_mode threshold voltage "inputs SEL, SCL,SDA,MUTE "inputs SEL, SCL,SDA,MUTE i 2.4 0 VDD1.8 0.8 V V V
8/29
TDA7501
Description of the input part
3
Description of the input part
On the input side, the TDA7501 (see Figure 3) connects the external audio and tuner signals to the four AD converters of the digital car radio signal processor TDA7500. The audio signals are adjusted by the input gain stage to the internal reference signal with 2V rms referred to 4.15V (=V33 *1.2575). The following CODEC interface attenuates the 2VRMS to 0.8Vrms referred to the CODEC's reference voltage of 1.65V which allows a DC coupling to the TDA7500.
Figure 3.
Input part.
CDL CDR BYPASS (2Vrms) TO OUTPUT PART
INGAIN BYP PHONE/NAVI-MIX 0..15dB 1dB STEP
CDL PHONE/FDL CASSL CASSR CDL+ CDCDR+ QDIFFSTEREO CDL CDR NAVI/FDR PHONE/NAVI-MIX CASSL MPX-RDS AM AM-LEVEL
INSELECT 1L
MUTE
INGAIN 1L 2Vrms 0..15dB 1dB STEP
CODEC-IF 4.15Vdc 2Vrms VOUT: 1.65Vdc 0.8Vrms VIN: 0.8Vrms OUT1L
PHONE+ FULL DIFFERENTIAL STEREO PHONE-
DIFF-MONO PHONE/NAVI MIX
CDR PHONE/FDL NAVI/FDR PHONE/NAVI-MIX CASSR MPX-RDS FM/DUAL-MPX AM-SPIKES
INSELECT 1R
NAVI+ NAVIAM-LEVEL
DIFF-MONO (QDiff-Stereo) LEVEL-SHIFT
MUTE
INGAIN 1R 2Vrms 0..15dB 1dB STEP
CODEC-IF 4.15Vdc 2Vrms VOUT: 1.65Vdc 0.8Vrms VIN: 0.8Vrms OUT1R
FM-LEVEL
LEVEL-SHIFT CDL PHONE/FDL NAVI/FDR PHONE/NAVI-MIX CASSL ENVELOPE DETECTOR AM AM-SPIKES FM-LEVEL AM-LEVEL MUTE INGAIN 2L 2Vrms 0..15dB 1dB STEP CODEC-IF 4.15Vdc 2Vrms VOUT: 1.65Vdc 0.8Vrms VIN: 0.8Vrms OUT2L INSELECT 2L
FM TUNERAM FM/AM-DIFF DUAL-MPX
FM
AM
AM-IF
MPX-RDS
CDR PHONE/FDL NAVI/FDR PHONE/NAVI-MIX CASSR MPX-RDS FM/DUAL-MPX AM-SPIKES
INSELECT 2R
MUTE
INGAIN 2R 2Vrms 0..15dB 1dB STEP
CODEC-IF VIN: 4.15Vdc 2Vrms VOUT: 1.65Vdc 0.8Vrms 0.8Vrms OUT2R
D00AU1201
9/29
Description of the input part
TDA7501
3.1
Input Stages
The device offers several input stages for the different signals which have to be handled by the system. A quasi differential input (see Figure 4) can be used for (external) CD changer. The two mono differential inputs allow the connection of phone & navigation (see Figure 5) or it could be used as fully differential stereo input. Additionally a single-ended stereo input is available for Cassette applications. The lower part of the input section is dedicated to the tuner signals. Another quasi differential input (see Figure 6) is used to connect AM and FM referred to the tuner reference (Tuner). This concept supports also double tuner systems. Also two seperate level inputs are present which are followed by level-shifters to allow the use of the TDA7500's ADCs. For AM noise blanking an envelope detector driven by the AM IF is also available. Figure 4. Quasi differential input-stage.
Figure 5.
Mono differential input-stage.
Figure 6.
Differential input-stage for AM/FM.
10/29
TDA7501
Description of the input part
3.2
Dual MPX mode
The TDA7501 is able to support a twin tuner concept via the Dual MPX Mode. In this configuration the FM pin and the AM-pin are acting as MPX1 and MPX2 inputs. The DC Voltage at the TUNER pin controls whether MPX1, both MPX signals or MXX2 is used to decode the stereo FM signal (see Figure 6 Please note that the thresholds have a hysteresis of 500mV. During this mode the high ohmic mute acts on both inputs in parallel. Furthermore, a background tuner on the internal AM path can be selected by software aswtching to one of the two MPX inputs. For the programming of the Dual MPX Mode see the programming section. Figure 7. Block diagram Dual MPX.
MPX2 (AM+) HIZ-MUTE 1 50K (D5/5) 15K CTRL (TUNER-) 50K 1 15K FM + MPX1 (FM+) HIZ-MUTE 1 50K WINDOWCOMPARATOR & LOGIC 15K 15K + 15K 15K (D4/5)
AM
D00AU1202
3.3
Additional quasi differential Input
The TDA7501 can be programmed to additional quasi-differential input by rearranging the configuration of the navigation and AM level inputs. Since the AM level input becomes the 2nd differential input, the level shift function is not available. For the programming of the navigation/AM level input configuration see the programming section. Figure 8. Additional quasi differential input simplified
15K NAVI-/QDIFF1100K 1 + 15K NAVI+/COM+ 100K D3/4 68K D3/4 AMLEVEL/QDIFF21 15K + 15K LEVEL/QDIFF2 1 33K 15K NAVI/QDIFF1 15K
D00AU1203
11/29
Description of the input part
TDA7501
3.4
Transfer function of the AM/FM level inputs
In the TDA7501 two level shift stages convert a tuner level (DC) signal to a unipolar output signal with respect to the Codec Interface reference, that is 1.65V. The FM level input can be programmed to a signal range of either 0 to 5V (Lo range) which is the default, or 0 to 6V (Hi range). The AM level input is fixed to the lower 0 to 5V input range. For the programming of the FM level input range see the programming section. Figure 9. AM/FM level inputs transfer function (DC)
Vout (V) 2.65 2.30 2.15 1.90 1.65
LO RANGE
D00AU1204
HI RANGE
0
1
2
3
4
5 Vin(V)
12/29
TDA7501
Description of the output part
4
Description of the output part
The TDA7501 has 6 independent outputstage with volume control. The first 4 (main) outputs have an input selector which allows to select besides the DAC outputs CD direct or Phone/Navigation-mix. In addition one can mix the SPKR1 with Phone/Navigation so that traffic or navigation announcements can bypass the DSP (see figure 8). The TDA7500 CODEC outputs have a maximum output voltage of 0.5Vrms . To obtain 4Vrms , (in the dual supply mode only) the signal is first amplified to have a reference amplitude of 2V rms. The following volume stage offers up to 15dB gain which gives along with the programmable 6dB gain in the output-stage enough overdrive capability. To achieve the maximum output swing of 4Vrms the device must be supplied with an additional supply of 12V. With a single supply (Vdd = VCC = 8.3V) 2.8Vrms are obtained at the output at maximum. Figure 10. Output part.
4.1
Overall gain structure
The overall gain structure of the TDA7501 can be shown in its target application together with the V225. The output part in level select (D6/4) offers an additional adaption to the DSP's output level
13/29
Description of the output part Figure 11. Level diagram.
INPUT PART
TDA7501
TDA7501
LEVEL SELECT
OUTPUT PART
INPUT GAIN
IN
0..15dB 1dB STEP
2Vrms 4.15Vdc 2Vrms 4.15Vdc
CODEC INTERFACE
TDA7500
0.9Vrms 1.65Vdc
GAIN +6dB or +12dB
VOLUME +15 .. -79dB
OUTPUT LINEDRIVERS 0/+6dB STEP
2Vrms (typ) 4.15Vdc
OUT
0.8Vrms 1.65Vdc
2Vrms 4.15Vdc
2Vrms 4.15Vdc or 4Vrms 6Vdc
D00AU1205
4.2
Speaker (linedriver) outputs
The Speaker outputs can be configured in three different operating modes: 1. 2. 3. - Internal reference mode with 0dB output gain, - External reference mode with 0dB output gain - External reference mode with 6dB output gain
Basically, in the internalreference mode the linedriver amplifier acts as a buffer with 0dB gain regardless of the output gain programmed by bit D0. Since the buffer tracks the internal generated reference, the OUTPUTREF pin may be left floating. In the external reference mode the linedriver amplifiers reference tracks the voltage present at the OUTPUTREF pin. This reference does not necessary have to be external to the device, it can also be generated by invoking the VCC/2 divider inside the TDA7501 (bit D1/6). In practice, the term external reference implied that the OUTPUTREF pin at least has to connect to an external capacitor. In the external reference mode, an additional gain of 6dB can be added by assessing bit D0. This provides a nominal 4VRMS output level in case the TDA7501 is powered from a dual supply (VDD = 8.3V). When fed from a single supply, only 2.8VRMS output level can be acheived. For the programming of output gain and reference selection see the programming section. Figure 12. Speaker (Linedriver) outputs simplified
D1/6 from VOLUME-STAGE 2Vrms 4.15Vdc 0dB buffer 2R 6dB R 3R 6dB D0/6 VREF OUTPUTREF
+ D1/6 VREF 2R R 3R D0/6 6dB 6dB
SPKROUT
D00AU1207
14/29
TDA7501
Reference concept
5
Reference concept
For the input section the TDA7501 generates the internal reference voltage by multiplying the V33 voltage by 1.2575. The V33 voltage is also buffered and fed back to the CODEC where it is used to generate all necessary references. For best performance it is recommended to filter the V33 reference pin by means of a passive second order lowpass as shown in Figure 13. This concept allows a direct DC coupling between the TDA7501 and the DSP because of the accurate matching of DC levels. On the output side the TDA7501 offers two main modes: a single supply and a dual supply mode.
5.1
Dual supply mode
In this mode the outputs are able to provide up to 4V rms with a minimum supply VCC of 12V as well as a output reference voltage set to half of VCC (bit D0 of the mode select byte set to '1'). If the switch D1/byte mode select is open the output reference voltage must be defined externally e.g. a zener diode with RC lowpass. If the switch is closed the reference voltage will be half of VCC and only an external capacitor has to be added.
5.2
Single supply mode
If VCC and Vdd are connected to a single supply the maximum possible output swing is about 2.8V rms . The output reference voltage pin can be left open or otherwise the internal voltage divider can be used to generate for the outputs a VCC/2 reference. Figure 13. Reference voltage generation
TDA7500 TDA7501
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Digital interface
TDA7501
6
Digital interface
The TDA7501 digital interface offers two different protocols: SPI and I2C. To select I2C-mode the SEL-pin has to beconnected to VDD. If the voltage at the SEL-pin is more than about 1V below the VDD voltage the interface switches to SPI-mode. In both cases the interface is able to work with a 3.3V microprocessor as well as with a 5V microprocessor. For details of both protocols refer to the programming section.
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TDA7501
SPI bus mode
7
7.1
SPI bus mode
Interface protocol
The TDA7501 SPI interface protocol comprises :

a subaddress and a sequence of n databytes
each consisting of 8 bits (see Figure 14). The interface accepts both a positiv (Cpol = 1, Cpha = 1) as well as a negativ (Cpol = 0, Cpha = 0) clocking scheme. However, the data transmitted has to be valid on the rising edges of the serial clock SCL. Figure 14. Timing diagram for the SPI bus mode.
SEL SCL Cpol=1 SCL Cpol=0 SDA
SA3 SA2 SA1 SA0 SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 DATA-n D2 D1 D0
D00AU1209
DATA
Table 5.
Symbol fSCLK Tsu Thld Twh Twl Tscl Trel tr tf Tsh
Switching characteristics (SPI mode)
Parameter Serial input clock frequency (SCL) Serial data setup time Serial data hold time Serial clock high time width Serial clock low time width Select (SEL) to select (SCL) falling setup time Select (SCL) to select (SEL) rising release time Data rise time Data fall time Chip select high time 200 Min. 0 40 40 100 100 200 200 2 2 Typ. Max. 4.0 Unit MHz ns ns ns ns ns ns ms ms ns
Figure 15. Timing diagram for switching characteristic
Tscl Tsu Thld Twh Twl Trel Tsh
SEL
SCL
SDA
SAx,Dy
D00AU1208
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I2C bus mode
TDA7501
8
8.1
I2C bus mode
Interface protocol
The interface protocol comprises:

a start condition (S) a chip address byte (write mode only) a subaddress byte a sequence of data (N-bytes + acknowledge) a stop condition (P)
CHIP ADDRESS
SUBADDRESS
DATA 1...DATA n
MSB S 1 0 0 0 1 1 0
LSB
MSB 0 I
LSB 0 SA3 SA2 SA1 SA0 ACK
MSB DATA
LSB
AK P C
0 ACK 0
ACK = Acknowledge S = Start P = Stop
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TDA7501
Software specification for both modes
9
9.1
Software specification for both modes
Auto increment
If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled.
9.2
Reset condition
A Power-On-Reset is invoked if the Supply-Voltage V dd is below than 3.5V. After POR the following data is written automatically into the registers of all subaddresses :
MSB 1 1 1 1 1 1 1
LSB 0
The programming after POR is marked bold-face in the programming tables. With this programming all the outputs are muted to their corresponding reference voltages.
9.3
Programming modes
Table 6.
MSB D7 D6 I D4 SA3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 SA2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SA1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Subaddresses
LSB Name SA0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Input selector 1L Input selector 1R Input selector 2L Input selector 2R Phone/Navigation Mode Select Configuration Output selector Volume 1L Volume 1R Volume 2L Volume 2R Volume 3L Volume 3R FM-level reserved Autoincrement mode off Autoincrement mode on must be "0"
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Software specification for both modes Table 7.
MSB D7 D6 D5 D4 D3 D2 D1
TDA7501
Input selector 1L..3R, bits D7 ..D3 (subaddresses 0..3)
LSB Function D0 mute off on gain 15dB 14dB 13dB 12dB 11dB 10dB 9dB 8dB 7dB 6dB 5dB 4dB 3dB 2dB 1dB 0dB
0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Table 8.
MSB D7 D6
Input selector 1L, bits D2 ..D0 (subaddresses 0)
LSB Function D5 D4 D3 D2 D1 D0 source select CDL Phone/FDL Navigation/FDR Phone/Navigation mix CassL MPX-RDS AM AM-level
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
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TDA7501 Table 9.
MSB D7 D6 D5 D4 D3 D2 D1
Software specification for both modes Input selector 1R, bits D2 ..D0 (subaddresses 1)
LSB Function D0 source select CDR Phone/FDL Navigation/FDR Phone/Navigation mix CassR MPX-RDS FM (or MPX1/MPX2 in Dual MPX mode) AM-spikes
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Table 10.
MSB D7 D6
Input selector 2L, bits D2 ..D0 (subaddresses 2)
LSB Function D5 D4 D3 D2 D1 D0 source select CDL Phone/FDL Navigation/FDR Phone/Navigation mix CassL AM FM-level AM-level
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Table 11.
MSB D7 D6
Input selector 2R, bits D2 ..D0 (subaddresses 3)
LSB Function D5 D4 D3 D2 D1 D0 source select CDR Phone/FDL Navigation/FDR Phone/Navigation mix CassR MPX-RDS FM (or MPX1/MPX2 in Dual MPX mode) AM-spikes
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
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Software specification for both modes Table 12.
MSB D7 D6 D5 D4
TDA7501
Phone navigation (subaddress 4)
LSB Function D3 D2 D1 D0 mix level phone/navigation 0/mute -1.6dB/-15.5dB -3.6/-9.6dB -6/-6dB -9.6/-3.6dB -15.5/-1.6dB mute/0dB mute Input configuration quasidifferential input (no level shift function) Navi & AM Level input gain 15dB 14dB 13dB 12dB 11dB 10dB 9dB 8dB 7dB 6dB 5dB 4dB 3dB 2dB 1dB 0dB
0 0 0 0 1 1 1 1 0
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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TDA7501 Table 13.
MSB D7 D6 D5 D4 D3 D2 D1
Software specification for both modes Mode select (subaddress 5)
LSB Function D0 AM-IF rectifier gain 18dB 15.5dB 12dB 6dB AM-IF rectifier corner frequency 14KHz 18.5KHz 28KHz 56KHz backkground tuner select (internal AMpath) FM-in (MPX1) AM-in (MPX2) Dual MPX mode on (control through Tuner- - voltage) off forced Dual MPX mode MPX1 (allows automatic selection) MPX2 (overwrites automatic selection) MPX1+ MPX2 (overwrites automatic selection) MPX1 (overwrites automatic selection)
0 0 1 1 0 0 1 1 0 1 0 1
0 1 0 1
0 1
0 1 0 0 1 1 0 1 0 1
Table 14.
MSB D7 D6
Configuration (subaddress 6)
LSB Function D5 D4 D3 D2 D1 D0 output gain 0dB +6dB reference voltage setting for output external reference / internal reference (V33*1.25) internal divider for output reference voltage connected to VCC/2 disconnected fast charge (switches at CD input) open closed Input level select (output power)12dB6d0
0 1 0 1 01
01 01
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Software specification for both modes Table 14.
MSB D7 D6 D5 01 D4 D3 D2 D1
TDA7501
Configuration (subaddress 6) (continued)
LSB Function D0 RDS-mute (high impedance)mutedunmuted mute pin function I"0" does not activate the output mute"1" activates the output mute mute pin function II"0" activates the high impedance mute"1" does not activate the high impedance mute
01
01
Table 15.
MSB D7 D6
Output selector (subaddress 7)
LSB Function D5 D4 D3 D2 D1 D0 source select SPKR 1L Bypass CDL Phone/Navigation mix / IN1L IN1L source select SPKR 1R Bypass CDL Phone/Navigation mix / IN1RI N1R source select SPKR 2L Bypass CDL mute IN2L source select SPKR 2R Bypass CDL mute IN2R
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 0 1
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TDA7501 Table 16.
MSB D7 D6 D5 D4 D3 D2 D1
Software specification for both modes Volume speaker outputs (subaddresses 8...13)
LSB Function D0
1 : 1 1 0 0 : 0 0 : 0 0 x
0 : 0 0 0 0 : 0 0 : 1 1 1
0 : 0 0 0 0 : 0 0 : 0 0 1
0 : 0 0 0 0 : 0 1 : 0 0 x
1 ; 0 0 0 0 : 1 0 : 1 1 x
1 ; 0 0 0 0 : 1 0 : 1 1 x
1 ; 0 0 0 0 : 1 0 : 1 1 x
1 ; 1 0 0 1 : 1 0 : 0 1 x
+15dB : +1dB 0dB 0dB -1dB : -15dB -16dB : -78dB -79dB Mute
Table 17.
MSB D7 D6
FM level range (subaddress 14)
LSB Function D5 D4 D3 D2 D1 D0
1
0
0 : 1
0 : 1
1
1 0 1
0...6Volts 0...5 Volts 0 Must be
1
1
1
1
The unused subaddresses 14/15 must be programmed to "11111110" to allow software compatibility to future extensions.
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Software specification for both modes Figure 16. Test board diagram
10K 3.3V 10F 6.8K V33 10F SIGGND 100nF CASSL 100nF CASSR 100nF CDL 100nF CDGND 100nF CDR 100nF PHONE+ 100nF PHONE100nF NAVI100nF NAVI+ 100nF FM 100nF AM 100nF MPX 100nF AM-IF 100nF TUNERCASSL 44 1 43 OUT1L 3.3nF
TDA7501
OUT1R
2 3
42
OUT2L
3.3nF
41
OUT2R
330pF
CASSR
4
40 39
ADCYDDREF IN1L 220nF
330pF
CDL+
5
TDA7500
220nF
CD-
6
38
IN1R
CDR+
7
37
IN2L
220nF
PHONE+
8
TDA7501
36
IN2R
220nF
PHONE-
9
35
IN3L
220nF
NAVI-
10
34 33 32 31 30 29 28
IN3R MUTE SDA SCL SEL SPKR1L
220nF
NAVI+
11
MUTE SDA SCL SEL OUTLF OUTRF OUTLR OUTRR OUTSWL OUTSWR 10K VCC 12V 6.8K 10F 6V
FM
14
AM
16
SPKR1R SPKR2L SPKR2R SPKR3L SPKR3R OUTPUTREF
MPX-RDS
17
27 26
AM-IF
18
25 24
TUNER-
15 12 13 FM-LEVEL GND 19 PGND 22 VDD 20 VCC 21
23
AM-LEVEL
10F
AM-LEVEL
FM-LEVEL
8.3V
12V
D00AU1210
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TDA7501
Package information
10
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 17. LQFP44 (10x10) mechanical data & package dimensions
mm DIM. MIN. A A1 A2 B C D D1 D3 E E1 E3 e L L1 k ccc 0.45 11.80 9.80 0.05 1.35 0.30 0.09 11.80 9.80 12.00 10.00 8.00 12.00 10.00 8.00 0.80 0.60 1.00 0.75 0.018 12.20 10.20 0.464 0.386 1.40 0.37 TYP. MAX. 1.60 0.15 1.45 0.45 0.20 12.20 10.20 0.002 0.053 0.012 0.004 0.464 0.386 0.472 0.394 0.315 0.472 0.394 0.315 0.031 0.024 0.039 0.030 0.480 0.401 0.055 0.015 MIN. TYP. MAX. 0.063 0.006 0.057 0.018 0.008 0.480 0.401 inch
OUTLINE AND MECHANICAL DATA
0(min.), 3.5(typ.), 7(max.) 0.10 0.0039
LQFP44 (10 x 10 x 1.4mm)
0076922 E
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Revision history
TDA7501
11
Revision history
Table 18.
Date 21-Jun-2004 22-Jun-2004 9-Sep-2004 15-Dec-2004 17-Jan-2007
Document revision history
Revision 1 2 3 4 5 Initial release. Minor revision, content edit. Minor revision, content edit. Minor revision, content edit. Package changed, layout change, text modifications Changes
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TDA7501
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